A dynamic semiconductor memory cell as used in DRAMs (dynamic random access memories) comprises a storage capacitor for storing data and an access transistor for accessing the data stored in the storage device.
Data is stored by charging or discharging the storage capacitor. In stacked capacitor type memory cells the capacitors are formed in a mold layer that covers a substrate surface of a semiconductor substrate.
Within the semiconductor substrate and adjacent to the substrate surface a field effect transistor (FET) is formed as access transistor. In a bit line sensing scheme the access transistor connects a storage electrode of the storage capacitor to a bit line when the cell is addressed.
During a write operation the storage electrode of the storage capacitor is loaded or unloaded according to the potential of the bit line. During a read operation the charge of the storage electrode is transferred to the bit line via the access transistor.
A capacitor dielectric separates the storage electrode and a backside electrode that acts as counter electrode. The backside electrode is connected to a fixed potential. In an array with a plurality of dynamic semiconductor memory cells the backside electrodes of the storage capacitors are connected to each other and form a cell plate.
Due to leakage phenomena charge flows from or to the storage electrode even if the memory cell is not addressed. Refresh cycles are required therefore for to recharge the storage capacitor and for to restore the data being stored therein. Increasing the amount of charge that may be stored in the capacitor may reduce the number of refresh cycles. Thus a larger surface area of the capacitor electrodes is required.
To achieve high packaging densities in a semiconductor memory circuit, the area being occupied by the projection of the storage capacitor on the planar semiconductor substrate surface should not be greater than the area that is occupied by the access transistor on the semiconductor substrate surface.
Increasing the height of the capacitor electrodes above the substrate surface enlarges the effective surface area of the capacitor electrodes. With decreasing design rules and smaller transistor areas, the height of the capacitor electrode increases.
In U.S. Patent Application Pub. No. 2005/0087789 A1, the disclosure of which is incorporated herein by reference, a storage capacitor for a dynamic semiconductor memory cell is described.
According to a first embodiment disclosed in the above document, the storage electrode of the storage capacitor is pad-shaped and forms a solid (not hollow) cylinder. The capacitor dielectric covers the solid pad-shaped storage electrode. The backside electrode covers the capacitor dielectric.
According to a second embodiment disclosed in the above document, the storage capacitor has a double-sided cup-shaped storage electrode. The cup-shaped storage electrode forms a hollow cylinder. The hollow cylinder is closed at the bottom end, which connects the storage electrode to a conducting structure in the adjacent substrate. The hollow cylinder is open at the other end. A capacitor dielectric covers both the inner and the outer vertical sidewalls of the hollow cylinder. The backside electrode covers the capacitor dielectric.
Both the pad-shaped storage electrode and the double-sided, cup-shaped storage electrode concept suffer from the occurrence of sticking or leaning during processing. The surface tension of etching and rinse fluids may cause the storage electrode to lean or to collapse. Leaning storage electrodes may result in electrical short circuits between neighboring memory cells.
According to a single-sided cup-shaped storage electrode concept, the storage electrode is formed exclusively on the inner sidewall and on the bottom portion of an opening in a mold layer. The capacitor dielectric covers the storage electrode. The backside electrode covers the capacitor dielectric within the opening of the mold layer and the surface of the mold layer. Contrary to the above discussed double-sided cup-shaped storage electrode type, the single-sided storage electrode is embedded in a mold layer during each process step of fabrication. Therefore, the single-sided cup-shaped storage electrode does not suffer from sticking and leaning problems.
For a ground area of the storage electrode of about 100 nm2 a height of the storage electrode of more than 4 μm may be required. Then, during formation of the storage capacitor, an opening has to be formed with an aspect ratio of depth to width of more than 100 to 1.
In U.S. patent application Ser. No. 11/039,740, the disclosure of which is incorporated herein by reference, a method is disclosed according to which two or more storage capacitors with pad-shaped storage electrodes are stacked on each other. The storage capacitors are formed successively, such that the pad-shaped storage electrode of the respective upper storage capacitor adjoins the pad-shaped storage electrode of the respective lower storage capacitor. The backside electrodes are connected to each other by means of a contact structure, such that the two or more stacked capacitors form a single capacitor. The maximum height of the resulting single capacitor is decoupled from the aspect ratios that occur during processing.
Further with smaller ground rules and ground area, the aspect ratio for the deposition of the last layer (i.e., the backside electrode material) increases significantly.
U.S. Patent Application Pub. No. US 2004/0217406 A1, the disclosure of which is incorporated herein by reference, refers to a storage electrode comprising a pad-shaped lower section and a cup-shaped upper section for to increase capacitance while reducing the occurrence of close contacts and leaning of the storage electrodes. Even if the cup-shaped upper section is perfectly aligned to the pad-shaped lower section, an edge or step results at the interface of the upper section and the lower section on the outer sidewall of the storage electrode. Then a problem occurs when high-k materials (e.g., HfSiOx or HfAlO) are used as capacitor dielectric. Increasing the deposition temperature enhances the electric properties of the layer of the high-k material but deteriorates the step coverage performance of the layer.
For these and other reasons there is a need for the present invention.